| Number | Title | Author 1 |
| 2 | A 500 MHz One volt 16 by 16 bit multiplier for DSP cores | C. Lemonds |
| 3 | Low-power FIR implementation using ternary coefficients | R. Hezar |
| 4 | Estimation of average energy consumption of ripple-carry adder based on maximum average carry chains | L.A. Montalvo |
| 6 | Digital upconversion architecture for quadrature modulators | P. Schaumont |
| 7 | ComBox: Library-based generation of VHDL modules | M. Vaupel |
| 9 | Efficient VLSI suited architectures for the discrete wavelet transform | S. Simon |
| 10 | Model-based architectural design and verification of embedded DSP systems - A RASSP approach | L-R Dung |
| 11 | Video DSP architecture and its application design methodology for sampling rate conversion | K. Nakamura |
| 12 | Real-time MPEG-2 software decoding with a dual-issue RISC processor | E. Holmann |
| 13 | An area effective cell-based channel decoder LSI for a digital satellite TV broadcasting | T. Kamada |
| 17 | SHARP: Efficient loop scheduling with data hazard reduction on multiple pipeline DSP systems | S. Tongsima |
| 18 | A 250 Msample/s programmable cascaded integrator-comp decimation filter | A. Kwentus |
| 21 | Low power storage exploration for H.263 video decoder | L. Nachtergaele |
| 22 | Scheduling for minimum memory accesses for low power applications | R. Saied |
| 23 | Hardware design of a Hough transform based 2D motion estimation system | H-L Li |
| 26 | Novel structures for serial multiplication over the finite field GF(2^m) | M.C. Mekhallalati |
| 27 | Design of a compact direct digital frequency synthesizer with 12-bit amplitude and 32-bit frequency resolution | G. Fischer |
| 29 | Adaptive CDMA receiver implementation for multipath and multiuser environments | L. Lucke |
| 31 | Low power parallel multipliers | E. de Angel |
| 32 | A parallel architecture for rapid prototyping of mechatronic algorithms by exploiting implicite fine-grain parallelism | M. D. Doan |
| 33 | Floating-point nonlinear DSP coprocessor cell -- Two cycle chip | V.K. Jain |
| 35 | Fixed-point error analysis and wordlength optimization of a distributed arithmetic based 8x8 2D-IDCT architecture | S. Kim |
| 36 | New motion estimation using low-resolution quantization for MPEG2 video encoding | S. Lee |
| 38 | A low power DSP engine for wireless communications | I Verbauwhede |
| 39 | LISA - Machine description language and generic machine model for HW/SW co-design | V. Zivojnovic |
| 43 | Memory module selection for high level synthesis | O. Sentieys |
| 45 | VLSI architectures for multiplication in GF(2^m) for application tailored digital signal processors | W. Drescher |
| 46 | High-Radix parallel dividers for VLSI signal processing | T. Aoki |
| 47 | An object based data cache with conflict free concurrent access as shared memory for a parallel DSP | J. Kneip |
| 50 | Calibration optimization and DSP implementation of microphone array for speech processing | A. Wang |
| 51 | A new implementation of 8x8 2-D DCT/IDCT | Y-P Lee |
| 52 | An integrated framework for optimizing transformations | S-H Huang |
| 54 | Parallel and pipelined architecture designs for distributed arithmetic-based recursive digital filters | Y-T. Hwang |
| 55 | Design issues for very-long-instruction-word (VLIW) VLSI video signal processors (VSPs) | S. Dutta |
| 57 | Parallel structures for joint channel estimation and data detection over fading channels | M.J. Omidi |
| 58 | Ultra-low power-domain-specific multimedia processors | A. Abnous |
| 59 | VLSI array architectures for pyramid vector quantization | B. Jung |
| 61 | Divide-and-conquer techniques for global throughput optimization | L. Guerra |
| 62 | A chip set for a ray-tracing engine | G.J. Hekstra |
| 63 | Maximizing the fault-tolerance of application specific programmable signal processors | K. Kim |
| 64 | Scalability of 2-D wavelet transform algorithms: analytical and experimental results on coarse-grain parallel computers | J.N. Patel |
| 65 | Microprocessor architecture design for low-cost low-power video decoding | K. Nadehara |
| 66 | A scalable architecture for 2-d discrete wavelet transform | J.C. Limqueco |
| 67 | A novel architecture and processor-level design based on a new matching criterion for video compression | H. Yeo |
| 68 | Logic synthesis of binary carry-save and mixed-radix arithmetics for digital signal processing | S.J. Bitterlich |
Last Update: 5/25/96
Name: K. Konstantinides