1996 IEEE Workshop on VLSI Signal Processing

Advance Program

8:50 am       Welcome - Introduction 
9:00 am       Keynote Speech   

             "Recent Advances in Mobile Video Communications" 
             Prof. Bernd Girod, Univ. of Erlangen, Germany.
          


9:45-10:15 am  Application Specific Processors (Poster Session) 
              (4 minute presentations)

              Chair: Earl Swartzlander, Univ. of Texas, Austin, USA.

• "An object based data cache with conflict free concurrent access as shared memory for a parallel DSP," J. Kneip, and P. Pirsch, Univ. of Hannover, Germany

• "Parallel and pipelined architecture designs for distributed arithmetic-based recursive digital filters," Y-T. Hwang, and C-L. Su, National Yunlin Inst. of Technology, Taiwan ROC.

• "Floating-point nonlinear DSP coprocessor cell -- Two cycle chip", V.K. Jain, and L. Lin, Univ. of South Florida, USA.

• "VLSI architectures for multiplication in GF(2^m) for application tailored digital signal processors," W. Drescher, and G. Fettweis, Dresden Univ. of Technology, Germany.

• "Novel structures for serial multiplication over the finite field GF(2^m)," M.C. Mekhallalati, and A.S. Ashur, Univ. of Nottingham, UK.

• "Design of a compact direct digital frequency synthesizer with 12-bit amplitude and 32-bit frequency resolution," G. Fischer, and N. Modadugu, Univ. of Rhode Island, USA.

• "High-Radix parallel dividers for VLSI signal processing," T. Aoki, H. Tokoyo, and T. Higuchi, Tohoku University, Japan.

10:15 - 10:30 am      Break and continuation of the poster session.  

11:00 am        Video Processors (Regular Session) 

                Chair: Wayne Wolf, Princeton Univ., USA

• "Design issues for very-long-instruction-word (VLIW) VLSI video signal processors (VSPs)," S. Dutta, K.J. O'Connor, A. Wolfe, and W. Wolf, Princeton University, USA.

• "Real-time MPEG-2 software decoding with a dual-issue RISC processor," E. Holmann, T. Yoshida, A. Yamada, and S. Uramoto, Mitsubishi Electric Co., Japan.

• "Low power storage exploration for H.263 video decoder," L. Nachtergaele, F. Catthoor, B. Kapoor, S. Janssens, and D Moolenaar, IMEC, Belgium

12:30 pm      Lunch 


2:00  pm      Computer-Aided Design (Regular Session) 

              Chair: Jef van Meerbergen, Philips Research, The Netherlands.

• " LISA - Machine description language and generic machine model for HW/SW co-design," V. Zivojnovic, S. Pees, and H. Meyr, Aachen Univ. of Technology, Germany

• "Divide-and-conquer techniques for global throughput optimization," L. Guerra, M. Potkonjak, and J. Rabaey, U.C. Berkeley, USA

• "Model-based architectural design and verification of embedded DSP systems - A RASSP approach," L-R Dung, V.K. Madisetti, and J.W. Hines, Georgia Institute of Technology and US Air Force Wright Labs, USA

3:30 - 3:50pm  Low power and Wireless Architectures (Poster Session)

                  (4 minute presentations)
          
                  Chair: John Eldon, Raytheon Electronics, USA.

• "Adaptive CDMA receiver implementation for multipath and multiuser environments," L. Lucke, H. Oie, and L.B. Nelson, Univ. of Minnesota,USA.

• "Scheduling for minimum memory accesses for low power applications," R. Saied and C. Chakrabarti, Arizona State Univ., USA

• "Low-power FIR implementation using ternary coefficients," R. Hezar and V.K. Madisetti, Georgia Tech., USA.

• "Estimation of average energy consumption of ripple-carry adder based on maximum average carry chains," L.A. Montalvo and K.K. Parhi, Univ. of Minnesota, USA.

• "Low power parallel multipliers," E. de Angel and E.E. Swartzlander Jr., Univ. of Texas at Austin, USA.

3:50 - 4:30 pm   Break and continuation of poster session.


4:30 - 6:00 pm    DSP Implementations (Regular Session) 
 
                 Chair: Keshab K. Parhi, Univ. of Minnesota, USA.

• "A chip set for a ray-tracing engine," G.J. Hekstra and E.F. Deprettere, Delft Univ. of Technology, The Netherlands.

• "Calibration optimization and DSP implementation of microphone array for speech processing," A. Wang, K. Yao, R.E. Hudson, D. Korompis, F. Lorenzelli, S. Soli, and S. Gao, UCLA and House Ear Institute, USA

• "A 250 Msample/s programmable cascaded integrator-comp decimation filter," A. Kwentus, O. Lee, and A.N. Willson Jr., UCLA, USA.

8:00 pm  Panel Discussion 

         Panel Chair: Bob Brodersen, U.C. Berkeley, USA.

• Panel: Is algorithm-to-architecture mapping useful beyond homework assignments ? (or is logic synthesis and general-purpose DSPs the answer to DSP implementations?)

Thursday, October 31

9:00 am    Keynote Speech  

	   "Packet Radio and the Microsystems Revolution,"
           Barry M. Leiner, Vice President, MCC, West Coast Laboratories.
          

9:45-10:15 am     Design Synthesis (Poster Session) 
                  (4 minute presentations)

               Chair: Mohammad Ibrahim, De Montfort Univ., UK. 
                

• "Logic synthesis of binary, carry-save and mixed-radix arithmetics for digital signal processing," S.J. Bitterlich and H. Meyr, RWTH Aachen, Germany

• "SHARP: Efficient loop scheduling with data hazard reduction on multiple pipeline DSP systems," S. Tongsima, C. Chantrapornchai, N.L. Passos, and E. H-M Sha, Univ. of Notre Dame, USA.

• "An integrated framework for optimizing transformations," S-H Huang and J.M. Rabaey, Univ. of California, Berkeley, USA

• "Memory module selection for high level synthesis," O. Sentieys, D. Chillet, J.P. Diguet, and J.L. Philippe, LASTI-ENSSAT,France.

• "Maximizing the fault-tolerance of application specific programmable signal processors," K. Kim, R. Karri, and M. Potkonjak, Univ. of Massachussetts, Amherst and UCLA, USA.

• "ComBox: Library-based generation of VHDL modules," M. Vaupel, T. Groetker, and H. Meyr, Aachen Univ. of Technology, Germany.

• "A parallel architecture for rapid prototyping of mechatronic algorithms by exploiting implicite fine-grain parallelism," M. D. Doan and M. Glesner, Darmstadt Univ. of Technology, Germany

10:15 - 11:00 am    Break and continuation of poster session 


11:00 am      Communication Circuits (Regular Session) 

              Chair: H. Meyr, Aachen Univ. of Technology, Germany.

• "Digital upconversion architecture for quadrature modulators," P. Schaumont, S. Vernalde, M. Engels, and I. Bolsens, IMEC/VSDM, Belgium.

• "Parallel structures for joint channel estimation and data detection over fading channels," M.J. Omidi, P.G. Gulak, and S. Pasupathy, Univ. of Toronto,Canada.

• "An area effective standard cell based channel decoder LSI for digital satellite TV broadcasting," T. Kamada, T. Fukuoka, Y. Nakai, Y. Nakakura, K. Ueda, K. Ota, T. Shiomi, and Y. Fukumoto, Matsushita Electric Industrial Co.,Japan.

12:30  pm    Lunch 


2:00 pm   Keynote Speech  

           "Technology for the Wireless Interconnection of 
            Wearable Personal Electronic Accessories " 
            Philip P. Carvey, BNN, Cambridge, MA.

2:45 pm   Architectures for Video Coding (Regular Session) 

             Chair: Leah Jamieson, Purdue University, USA.

• Invited Talk: "A DSP Architecture for the seven multimedia functions: The chromatic research Mpact", Robert E. Owen, Chromatic Research, Inc., USA.

3:15 - 3:30 pm   Break. 

3:30 - 5:30 pm   Session Continues 

• "VLSI array architectures for pyramid vector quantization," B. Jung and W.P. Burleson, Univ. of Massachusetts, Amherst, USA.

• "Hardware design of a Hough transform based 2D motion estimation system," H-L Li and C. Chakrabarti, Arizona State Univ.,USA.

• "A scalable architecture for 2-D discrete wavelet transform," J.C. Limqueco and M.A. Bayoumi, Univ. of Southwestern Louisiana, USA.

• "Scalability of 2-D wavelet transform algorithms: analytical and experimental results on coarse-grain parallel computers," J.N. Patel, A.A. Khokhar, and L.H. Jamieson, Purdue University, USA.

6:00 - 10:00 pm    Dining Cruise of the San Francisco Bay 

Friday, November 1

9:00 am Keynote Speech 

           "Technology Trends and Challenges for Wireless Mobility
	   and Connectivity"            
           Pradeep Shah, TI Fellow, Personal Systems Laboratory,
           Texas Instruments.
          

9:45 - 10:15 am Architectures for Video Coding (Poster Session) 
                  (4 minute presentations)

                  Chair: Peter Pirsch, Univ. of Hannover, Germany. 

• "Efficient VLSI suited architectures for the discrete wavelet transform," S. Simon, P. Rieder, and J.A. Nossek, Technical University Munich,Germany

• "Fixed-point error analysis and wordlength optimization of a distributed arithmetic based 8x8 2D-IDCT architecture," S. Kim and W. Sung, Seoul National University ,Korea

• "A new implementation of 8x8 2-D DCT/IDCT," Y-P. Lee, L-G. Chen, M-J. Chen, and C-W. Ku, National Taiwan University, Taiwan ROC.

• "Video DSP architecture and its application design methodology for sampling rate conversion," K. Nakamura, M. Kurokawa, A. Hashiguchi, H. Okuda, S. Iwase, and T. Yamazaki, Sony Corporation,Japan

• "New motion estimation using low-resolution quantization for MPEG2 video encoding," S. Lee, J.M. Kim, and S-I. Chae, Seoul National Univ.,Korea.

• "Microprocessor architecture design for low-cost low-power video decoding," K. Nadehara, H.J. Stolberg, M. Ikekawa,E. Murata, and I. Kuroda, NEC Corporation,Japan.

• "A novel architecture and processor-level design based on a new matching criterion for video compression," H. Yeo and Y.H. Hu, Univ. of Wisconsin-Madison,USA.

10:15 - 11:00 am  Break and continuation of poster session. 


11:00 am   Low-power design for wireless communications 
              (Regular Session)

              Chair: Ichiro Kuroda, NEC, Japan

• "Ultra-low-power domain-specific multimedia processors," A. Abnous and J. Rabaey, U.C. Berkeley,USA.

• "A low power DSP engine for wireless communications," I. Verbauwhede, M. Touriguian, K. Gupta, J. Muwafi, K. Yick, and G. Fettweis, TCSI Corporation,USA.

• "A 500 MHz, one volt, 16 by 16 bit multiplier for DSP cores," Carl Lemonds, Texas Instruments, USA

12:30 pm    Closing Remarks 
            Lunch

          End of the workshop.